For supported device families, you can also view internal registers and look-up tables (LUTs) inside logic cells (LCELLs), and registers in I/O atom primitives. The Technology Map Viewer shows the hierarchy of atom primitives (such as device logic cells and I/O ports) in the design. The Intel® Quartus® Prime Technology Map Viewer provides a technology‑specific, graphical representation of FPGA designs after Analysis and Synthesis or after the Fitter maps the design into the target device.
